ENIAC: 20 digits per register × 10 registers × (4 bits to 1 byte) → 20 × 10 × 0.5 = 100 bytes? No.

Wed, 29 Apr 2026 19:12:07 +0000

Understanding ENIAC’s Memory Architecture: Clarity Amid Common Misconceptions The ENIAC (Electronic Numerical Integrator and Computer), developed in the 1940s, stands as a monumental achievement in early computing history. Yet, debates persist—especially around how its memory architecture is interpreted, often leading to misunderstandings like the flawed calculation: 20 digits per register × 10 registers × (4 bits to 1 byte) = 100 bytes. This equation misrepresents ENIAC’s actual memory encoding and data handling, so let’s unpack the truth behind ENIAC’s design. ### ENIAC’s Memory System: Digits, Registers, and Bits At its core, ENIAC was not a modern stored-program computer like EDVAC or von Neumann machines. Instead, it used a specialized, experimental design focused on rapid numerical computation—primarily for artillery firing tables during WWII. Its memory subsystem was built differently: